The present invention relates to SiC-MISFET formed using a SiC body, and more particularly relates to a storage-type SiC-MISFET and a method for fabricating a storage-type SiC-MISFET.
Silicon carbide (SiC) has a structure in which Si and C are bounds to each other with a composition ratio of 1:1, and is a wide bandgap semiconductor material which has a wider bandgap, a greater hardness, and a higher resistance to chemicals, compared to Si. SiC has higher breakdown field, even compared to other wide bandgap semiconductor materials. Therefore, application of SiC to low-loss power devices is expected. SiC includes many polytypes, such as cubic 3C-SiC, hexagonal 6H-SiC, 4H-SiC and the like. Among these polytypes, it is 6H-SiC or 4H-SiC that is generally used to fabricate a SiC-MISFET for practical use. Then, a substrate including a plane almost in accordance with the (0001) plane which is vertical to the crystallographic axis, i.e., a c-axis, as the principal surface has been widely used.
A SiC semiconductor device is formed by using an epitaxial layer formed on a SiC substrate as an active region and providing necessary regions in the active region according to the type of the active region. Among semiconductor devices, in the case of an FET, source/drain regions and a gate region are provided. Specifically, in a SiC-MISFET, i.e., an MIS (metal/insulation film/semiconductor) type FET, an MOSFET of the MOS (metal/oxide film/semiconductor) type using an oxide film formed as a gate insulation film by thermal oxidation has been widely known, in general.
On a Si layer, a silicon oxide film which is to be an excellent gate insulation film is formed by thermal oxidation. However, in the case of SiC layer, since C exists, in addition to Si, it is very difficult to form an excellent oxide film through regular oxidation. Specifically, since C exists in a silicon oxide film formed on the SiC layer, an interface level which traps a carrier with fixed charge is formed around the interface between a Si layer and an oxide film. For this reason, in an inversion type MISFET, only very small channel mobility of a carrier can be achieved in an inversion layer to be a channel layer through which current flows. Therefore, it is very difficult to make a large current flow in a SiC-MISFET. In order to solve this problem, in a power SiC-MISFET, a structure in which a storage-type channel layer containing an impurity of the same conductive type as that of a source/drain region is provided is generally used. Such MISFETs are called storage-type (or accumulation-type) SiC-MISFET (SiC-ACCUFET).
FIG. 9 is a cross-sectional view illustrating the structure of a general storage-type SiC-MISFET which has been conventionally used. As shown in FIG. 9, the general storage-type SiC-MISFET includes a SiC substrate 101, a first epitaxial layer 102a epitaxially grown on the principal surface of the SiC substrate 101, a second epitaxial layer 102b epitaxially grown on the first epitaxial layer 102a. The first epitaxial layer 102a includes an n-type body section 102c containing an n-type impurity (dopant) formed on the principal surface of the SiC substrate 101, a p-type well region 103 formed by implanting ions of a p-type impurity into the n-type body section 102c, and a heavily doped contact layer 109 containing the p-type impurity at a higher concentration than that in the well region 103. Moreover, the epitaxial layer 102b is formed so that part thereof extends over the well region 103 and the n-type body section 102c. The part of the epitaxial layer 102b forms a SiC channel layer 105, i.e., a storage-type channel layer containing an n-type impurity. Furthermore, the general storage-type SiC-MISFET includes an n-type source region 104 formed by implanting ions of an n-type impurity into parts of the second epitaxial layer 102b and the well region 103. Moreover, the general storage-type SiC-MISFET includes a gate insulation film 106 provided on the SiC channel layer 105, a gate electrode 113 formed on the gate insulation film 106, a source electrode 111 which forms an ohmic contact with the source region 104 and the heavily doped contact layer 109, and a drain electrode 112 which forms an ohmic contact with a surface of the SiC substrate 101 opposing to the principal surface (back surface) thereof The source region 104 is formed so as to overlap with the gate electrode 113 when viewed from the top and be in contact with the heavily doped contact layer 109 (e.g., see Japanese Laid Open Patent Publication No. 2001-144292).